1. Field of the Invention
The present invention relates to a method of driving a display device in which each pixel has a thin film transistor (hereinafter referred to as TFT). Specifically, the present invention relates to a method of driving a display device having an electro luminescence element, which is attracting attention as a light emitting element. The invention also relates to information equipment that use this driving method for a display device.
2. Description of the Related Art
A conventional method of driving a display device that has a light emitting element is described.
Shown here as an example of the light emitting element is an element in which an anode and a cathode sandwich an organic compound layer that emits light by electro luminescence effect upon application of the electric field (EL element).
The term EL element here refers to both an element that utilizes light emission (fluorescence) by shift from singlet exciton to the base state and an element that utilizes light emission (phosphorescence) by shift from triplet exciton to the base state.
An organic compound layer includes a hole injection layer, a hole transporting layer, a light emitting layer, an electron transporting layer, an electron injection layer, and the like. The basic structure of a light emitting element is a laminate of an anode, a light emitting layer, and a cathode layered in this order. The basic structure can be modified into a laminate of an anode, a hole injection layer, a light emitting layer, an electron injection layer, and a cathode layered in this order, or a laminate of an anode, a hole injection layer, a hole transporting layer, a light emitting layer, an electron transporting layer, an electron injection layer, and a cathode layered in this order.
A display device having a conventional light emitting element is described with reference to circuit diagrams in FIGS. 13 and 14 which illustrate examples of structures of pixel and pixel portion.
FIG. 14 shows the structure of a pixel portion.
A pixel portion 1401 has x columns of pixels and y rows of pixels which form a matrix. Each of the pixels is denoted by 1400. The symbols x and y denote arbitrary natural numbers.
The pixel portion 1401 is composed of source signal lines S1 to Sx, gate signal lines G1 to Gy, and power supply lines V1 to Vx, and each pixel in the pixel portion has a switching TFT 141, a driving TFT 142, a storage capacitor 143, and a light emitting element 144.
The storage capacitor 143 is not indispensable if the device makes a positive use of a parasitic capacitance of a gate of the driving TFT 142 or the like.
Signals from a source signal line driving circuit (not shown in the drawing) are inputted to the source signal lines S1 to Sx. Signals from a gate signal line driving circuit (not shown in the drawing) are inputted to the gate signal lines G1 to Gy. A constant electric potential is given to the power supply lines V1 to Vx.
The structure of each pixel 1400 in FIG. 14 is described next with reference to FIG. 13.
In each pixel, a gate signal line G that is one of the gate signal lines G1 to Gy is connected to a gate electrode of the switching TFT 141. The switching TFT 141 has a source region and a drain region one of which is connected to a source signal line S, namely, one of the source signal lines S1 to Sx, and the other of which is connected to a gate electrode of the driving TFT 142. The driving TFT 142 has a source region and a drain region one of which is connected to a power supply line V, namely, one of the power supply lines V1 to Vx, and to one of electrodes of the storage capacitor 143, and the other of which is connected to one of electrodes of the light emitting element 144. The other electrode of the storage capacitor 143 is connected to power supply line V, namely, one of the power supply lines V1 to Vx. Here, being connected means being in electrically conductive state.
Of an anode and a cathode of the light emitting element 144 in the pixel 1400, the one that is connected to the driving TFT 142 is called a pixel electrode and the other is called an opposite electrode.
The operation of each pixel 1400 is described in detail below. The description employs reference symbols in FIGS. 13 and 14.
In a certain period, one of the gate signal lines G1 to Gy is selected first. Every switching TFT 141 whose gate electrode is connected to the selected gate signal line is turned ON. Here, a TFT being turned ON means that the gate/source voltage (hereinafter referred to as gate voltage) of the TFT turns the drain/source thereof conductive. A selected signal line refers to a signal line receiving a signal electric potential to turn ON a TFT whose gate electrode is connected to the signal line.
Signals inputted from the source signal line driving circuit to the source signal line are inputted to the gate electrode of the driving TFT 142 through the drain/source of the switching TFT 141 that has been turned ON. The electric potential given to the gate electrode of the driving TFT 142 is held in the storage capacitor 143. The signals inputted to the gate electrode of the driving TFT 142 turn the driving TFT 142 ON to cause a current to flow into the light emitting element 144 through the drain/source of the driving TFT 142 from the power supply line. Then the light emitting element 144 emits light at a luminance according to the amount of current it receives.
Driving methods for a display device are roughly divided into analog methods and digital methods. The analog methods as defined in this specification are methods of displaying an image by inputting analog signals to source signal lines. The digital methods as defined herein are methods of displaying an image by inputting digital signals to source signal lines.
An analog driving method is described first.
FIG. 18 shows a block diagram of an analog display device.
In FIG. 18, the display device is composed of a driving circuit portion and a pixel portion 1800. The driving circuit portion consists of a source signal line driving circuit 1801 and a gate signal line driving circuit 1807. The source signal line driving circuit 1801 and the gate signal line driving circuit 1807 are respectively placed only on one side of the pixel portion 1800 in FIG. 18. However, the pixel portion 1800 may have the source signal line driving circuit 1801 on each side thereof and may have the gate signal line driving circuit 1807 on each side thereof. This arrangement is preferred in terms of drive efficiency and reliability of the display device.
Next, a detailed description is given on the structure of the source signal line driving circuit 1801.
In an analog method, video signals inputted from the external to the source signal line driving circuit 1801 may be analog signals or digital signals. When digital signals are inputted from the external to the source signal line driving circuit 1801 and analog signals are to be outputted to the source signal lines, the digital signals have to be converted into analog signals by a digital/analog converter (hereinafter referred to as DAC) in the source signal line driving circuit or before output of the source signal line driving circuit is inputted to the source signal lines.
The driving circuit shown in the block diagram of FIG. 18 receives digital video signals from the external to input analog signal voltage to the source signal lines.
The source signal line driving circuit 1801 is composed of a shift register 1802, a latch circuit (hereinafter referred to as LAT) 1 (denoted by 1803), an LAT2 1804, and a DAC 1805.
The amount of information digital video signals have are n (n is an arbitrary natural number) bits.
Digital video signals of the respective bits out of n bits are inputted to the LAT1 1803. Digital video signals inputted from the external are subjected to serial/parallel conversion in advance and groups of n-bit signals to be sent to their respective source signal lines are simultaneously inputted to the LAT1 1803. Input of signals for the first source signal line S1 is followed by input of signals for the second source signal line S2, and similar operation is repeated until signals for the x-th source signal line Sx are inputted to complete receiving signals for x source signal lines. In this way signals for one horizontal period are all inputted to the LAT1 1803. The signals held in the LAT1 1803 are then sent to the LAT2 at once in response to a latch pulse LS.
When the source signal line driving circuit 1801 for outputting signals to x source signal lines handles n-bit digital video signals, the LAT1 1803 and the LAT2 1804 each have to store xn bits digital video signals.
The n-bit digital video signals to be sent to their respective source signal lines are held in the LAT2 1804 and their digital signal voltages VD are inputted to the DAC 1805 to be converted into corresponding analog signal voltages. The source signal line driving circuit 1801 thus outputs analog signal voltages to the source signal lines.
A case of driving pixels by an analog method is described. The description is given with reference to the pixel circuit diagrams in FIGS. 13 and 14.
In analog driving, signals inputted to source signal lines are expressed as analog voltages. These analog signals are inputted to the gate electrode of the driving TFT 142 through the switching TFT 141 that has been turned ON and change the electric potential of the gate electrode of the driving TFT 142. This causes a change in gate voltage of the driving TFT 142 and a drain current flows in an amount according to the changed gate voltage into the light emitting element 144.
A driving method for this analog display-device is explained with reference to timing charts of FIGS. 15A and 15B. Also reference is made to FIG. 18.
In the timing chart, a period necessary for preparing display of one image is expressed as a frame period (F). Here the length of one frame period is set to about 1/60 second. With this length, human eye does not see flickering in animation displayed.
Operations up through inputting analog signal voltages to the source signal lines S1 to Sx at once are described first.
In FIG. 15A, digital signal voltages VD of groups of n-bit signals are simultaneously inputted to the LAT1 1803 of the source signal line driving circuit 1801 in response to sampling pulses from the shift register 1802 (during the sampling period in FIGS. 15A and 15B). After the sampling period, the digital signal voltages VD held in the LAT1 1803 are inputted to the LAT2 1804 at once in response to latch pulse LP to be held in the LAT2.
After outputting the signals to the LAT2 1804, the LAT1 1803 starts holding digital video signals VD for the next horizontal period in order.
The signal voltages inputted and held in the LAT2 1804 are inputted to the DAC 1805 to be converted into corresponding analog signal voltages. This digital/analog conversion processing is conducted in the retrace period after the sampling period. The signal voltages subjected to analog conversion are inputted to the source signal lines S1 to Sx at once.
The description above is about the operations up through inputting analog signal voltages to the source signal lines S1 to Sx at once.
Described next are operations of inputting to pixels the analog signal voltages inputted to the source signal lines.
FIG. 15B is a timing chart illustrating pixels in horizontal periods respectively associated with the gate signal lines. In a first frame period F1, the gate signal lines G1 to Gy are selected in order. During one gate signal line is selected, analog signal voltages are inputted to the source signal lines S1 to Sx at once.
Thus the analog voltages inputted to the source signal lines are inputted to the gate electrodes of the driving TFTs in the pixels that are connected to the selected gate signal line. A period in which this operation takes place is called a writing period.
A period in which a light emitting element emits or does not emit light in accordance with signals inputted during the writing period is called a display period.
The length of writing period is the same in each horizontal period but the starting point of the writing period varies from one horizontal period to another. The length of display period is the same in each horizontal period but the starting point of the display period varies from one horizontal period to another.
The lengths of writing period and display period are set so that the writing period of the preceding frame period does not overlap the writing period of the following frame period.
A display period is started as soon as signals are inputted in a writing period in each horizontal period.
In this way analog signal voltages are inputted to all the pixels to display one image.
The description on the driving method for the analog display device is concluded as above.
In an analog driving method, the driving TFT 142 usually operates in a range in which the drain current is changed greatly by a change in gate voltage. This range corresponds to the vicinity of the saturation range. For conveniences' sake, it is assumed here that the driving TFT 142 operates in the saturation range.
However, in an analog driving method as this, fluctuation in characteristic of the switching TFT 141 and the driving TFT 142 makes the amount of current flowing into the light emitting element 144 vary to cause uneven display.
To counter this problem, digital driving methods have been proposed.
A digital driving method is described next.
The following description is about a case of digitally driving the pixels structured as shown in FIGS. 13 and 14.
Here the switching TFT 141 may be an n-channel TFT or a p-channel TFT and the same applies to the driving TFT 142. When the anode of the light emitting element 144 serves as the pixel electrode whereas the cathode serves as the opposite electrode, the driving TFT 142 is preferably a p-channel TFT. When the cathode of the light emitting element 144 serves as the pixel electrode whereas the anode serves as the opposite electrode, on the other hand, it is preferable to use an n-channel TFT for the driving TFT 142.
This is because it is desirable for the driving TFT 142 to operate with the electric potential of its source region fixed.
To simplify the explanation of the digital driving method, the switching TFT 141 and the driving TFT 142 here are both n-channel TFTs.
The operation of the pixels is described below.
When signals are inputted to a gate signal line, the signals are inputted to the gate electrode of each switching TFT 141 that is connected to the gate signal line. The signal voltages of the signals are set to a level that turns the switching TFT 141 ON when the signals are inputted to the gate electrode of the switching TFT 141.
Digital driving and analog driving display devices are identical in terms of using signals inputted to a gate signal line to turn ON or OFF the switching TFT.
In digital methods, signals inputted to source signal lines are ‘1’ or ‘0’ and have either Hi voltage or Lo voltage.
Here, a ‘1’ signal corresponds to Hi signal voltage and a ‘0’ signal corresponds to Lo signal voltage.
In a pixel whose switching TFT 141 is turned ON, digital video signals inputted to the source signal lines are inputted to the gate electrode of the driving TFT 142. If the inputted digital video signals are Hi signals and the voltage of Hi signal is set in advance to the level that turns the driving TFT 142 ON upon input of Hi signal to the gate electrode of the driving TFT 142, a current flows into the light emitting element 144 from the power supply line V.
Here, a writing period is a period for inputting digital voltages that have been inputted to source signal lines to the gate electrode of the driving TFT of a pixel that is connected to a selected gate signal line.
A period in which a light emitting element emits or does not emit light in accordance with signals inputted during the writing period is called a display period.
The description above is about the operation of pixels in digital methods.
Described next is a gradation display method in digital methods.
Digital methods are divided into area ratio gradation methods, time ratio gradation methods, and others.
In area ratio gradation methods, one pixel is divided into a plurality of sub-pixels and whether or not light is emitted is decided for each sub-pixel. The luminance of one pixel is set by the total area of its sub-pixels that are chosen to emit light.
On the other hand, in time ratio gradation methods, a period for displaying one image is divided into a plurality of periods and the gradation of a pixel is determined by the length of time during which the pixel emits light.
A detailed description is given here on a time ratio gradation method. Reference is made to the timing chart of FIG. 16, the block diagram of FIG. 19, and the pixel portion circuit diagram of FIG. 14. The driving method described here obtains gradations using n-bit digital video signals.
The structure of a display device that uses the time ratio gradation method is described first. The description is given with reference to the block diagram of FIG. 19.
In FIG. 19, the display device is composed of a source signal line driving circuit 1901, a gate signal line-driving circuit 1907, a time ratio gradation data signal generating circuit 1908, and a pixel portion 1900. The source signal line driving circuit 1901 is composed of a shift register 1902, an LAT1 1903, and an LAT2 1904.
The operation of the display device structured as shown in FIG. 19 is described with reference to the timing chart of FIG. 16. The pixel portion and its components are denoted by the symbols used in FIG. 14.
In the timing chart, a period necessary for preparing display of one image is expressed as a frame period (F). Here the length of one frame period is set to about 1/60 second. With this length, human eye does not see flickering in animation displayed.
One frame period is divided into n sub-frame periods SF1 to SFn. The sub-frame period SF1 is divided into a writing period Taa1 and a display period Ts1.
In FIG. 16, a writing period Taa in each sub-frame period is the sum of a writing period Ta of a first horizontal period to a writing period Ta of the y-th horizontal period. In other words, the sum of writing periods (periods for writing signal into pixels) respectively associated with the first gate signal line to the y-th gate signal line is the writing period Taa of each sub-frame period.
The operation in the sub-frame period SF1 of the frame period F1 is described first. Here, the sub-frame period SF1 is the period for the first bit signal (uppermost bit digital signal). In this specification, the first bit is the uppermost bit and the n-th bit is the lowermost bit.
Digital signal voltages VD are inputted to the LAT1 1903 of the source signal line driving circuit 1901 through the time ratio gradation data signal generating circuit 1908. The time ratio gradation data signal generating circuit 1908 converts digital video signals into signals for displaying an image by a time ratio gradation method.
In response to sampling pulses from the shift register 1902, the source signal line driving circuit 1901 holds the first bit signal of the digital video signals VD in the LAT1 1903. Thereafter, the signals held in the LAT1 1903 are inputted to the LAT2 1904 at once in response to latch pulse LP to be outputted to the source signal lines.
If the display device is to input digital video signals to x source signal lines, it is sufficient if the LAT1 1903 and LAT2 1904 each can hold x bits digital video signals.
Assume that the gate signal line G1 is selected when the digital video signals are outputted to the source signal lines. Then the signals inputted to the source signal lines S1 to Sx are held in the storage capacitor 143 of each pixel in which the gate electrode of the switching TFT 141 is connected to the gate signal line G1.
In the writing period Taa1 for digital signals of the first bit, the electric potential of the opposite electrode of the light emitting element 144 is kept at almost the same level as the electric potential of the power supply lines V1 to Vx. Therefore the light emitting element 144 receives no current and does not emit light even when the driving TFT 142 is turned ON by the digital signals inputted to the source signal lines S1 to Sx.
After outputting the signals to the LAT2 1904, the LAT1 1903 starts holding digital video signals VD for the next horizontal period in order. Then the digital signals held in the LAT1 1903 are inputted to the LAT2 1904 at once in response to latch pulse LP to be outputted to the source signal lines S1 to Sx.
At this point, the gate signal line G2 is selected and the signals inputted to the source signal lines S1 to Sx are held in the storage capacitor 143 of each pixel in which the gate electrode of the switching TFT 141 is connected to the gate signal line G2. In the writing period Taa1, the above operation is repeated to select the gate signal lines G1 to Gy in order and input digital video signals to pixels. The inputted signals are held in the pixels. When the signals are inputted to all the pixels, the writing period Taa1 is ended. Then in the display period Ts1 for the first bit, the electric potential of the opposite electrode of the light emitting element 144 is changed such that the difference between that and the electric potential of the power supply lines V1 to Vx is large enough to cause the light emitting element 144 to emit light. The light emitting element 144 thus emits light only in each pixel whose driving TFT 142 is turned ON by the signals inputted from the source signal lines S1 to Sx.
Next, the electric potential of the opposite electrode of the light emitting element 144 is returned to almost the same level as the electric potential of the power supply lines V1 to Vx and the light emitting element 144 stops emitting light in every pixel. A writing period Taa2 in the second sub-frame period SF2 is thus started.
In the second sub-frame period, the gate signal lines G1 to Gy are selected in order similar to the first sub-frame period. This time, digital signals for the second bit are inputted to the gate electrode of the driving TFT 142 through the switching TFT 141. When the digital signals are inputted to all the pixels, the writing period Taa2 is ended. Then in the display period Ts2, the electric potential of the opposite electrode is changed such that the difference between it and the electric potential of the power supply lines V1 to Vx is large enough to cause the light emitting element 144 to emit light. The light emitting element 144 thus emits light in each pixel whose driving TFT 142 is turned ON.
Similar operation is conducted for the rest of digital signals until digital signals for the n-th bit are processed to complete the sub-frame periods SF1 to SFn. One frame period is thus finished. The lengths of the display periods Ts1 to Tsn of the sub-frame periods SF1 to SFn are set, for example, in accordance with the bits of signals inputted in the respective sub-frame periods and satisfy Tsn: Tsn−1: . . . : Ts3:Ts2:Ts1=20:21:22: . . . :2n−2:2n−1. The writing periods Taa1 to Taan each have the same length.
The gradation of a pixel in one frame period is determined by the sum of lengths of display periods in the one frame period in which the light emitting element 144 of the pixel emits light. When n=8, for instance, the luminance of a pixel is 100% if the pixel emits light in all of the display periods. If the pixel emits light in Ts8 and Ts7, the luminance thereof is 1%. If the pixel emits light in Ts6, Ts4, and Ts1, the luminance thereof is 60%.
Described above is the basic method in the time ratio gradation driving method.
Another method in the driving method is to allow pixels emit light for a display in the writing periods Taa1 to Taan as well as display periods.
In this method, the electric potential of the opposite electrode of the light emitting element 144 is set such that the difference between that and the electric potential of the power supply lines V1 to Vx is large enough to cause the light emitting element 144 to emit light also in the writing periods Taa1 to Taan. In other words, the display device is driven without changing the electric potential of the opposite electrode during one frame period in this method. A timing chart of this driving method is shown in FIG. 17.
In a writing period Taj (j is a natural number equal to or smaller than n) of one sub-frame period, the gate signal line G1 is selected to input signals to pixels on Row One (the first horizontal period). The pixels on Row One start or stop emitting light as soon as the signals are inputted in accordance with the inputted signals. The gate signal line G2 is selected next and signals are inputted to each pixel having a switching TFT whose gate electrode is connected to G2 (pixels on Row Two) (the second horizontal period). The pixels on Row Two start or stop emitting light as soon as the signals are inputted in accordance with the inputted signals. After conducting the above operation for all of the gate signal lines G1 to Gy is finished and the first to y-th horizontal periods are completed, one sub-frame period is ended.
In a sub-frame period, a period for writing in pixels connected to one gate signal line and a period for writing in pixels connected to another gate signal line are both denoted by Ta.
In the timing chart of FIG. 17, the starting point of writing signals in pixels varies between horizontal periods in a sub-frame period and therefore the starting point for a pixel to emit light also varies between horizontal periods. However, the length of the writing period Ta in one horizontal period is the same as the length of the writing period Ta in another horizontal period. Also, in a sub-frame period, the length of the display period Ts in one horizontal period is the same as the length of the display period Ts in another horizontal period.
In the above driving method, the lengths of the sub-frame periods SF1 to SFn may be set in accordance with the bits of signals inputted in the respective sub-frame periods and satisfy SFn:SFn−1: . . . :SF3:SF2:SF1=20:21:22: . . :2n−2:2n−1, for example.
The description given in the above is about a digital gradation display method.
Now, a drive range of a driving TFT of a pixel in the digital method is shown in the graph of FIG. 28. For comparison, the operation range of the driving TFT 142 in the analog driving method described above is also shown in the graph.
In the analog method, the driving TFT operates in the vicinity of the saturation range.
On the other hand, the driving TFT in the digital method operates in a range equal to or lower than the threshold where no drain current flows and in a linear range. This makes it possible to use the switching TFT 141 and the driving TFT 142 as switches.
Therefore, in the digital driving method, fluctuation in characteristic of the switching TFT 141 and the driving TFT 142 does not cause much variation in the amount of current flowing into the light emitting element 144. Uneven display due to fluctuation in characteristic of the switching TFT 141 and the driving TFT 142 thus can be reduced.
However, the above digital method has the following problems.
One problem is that the driving circuits consume a large amount of power in the digital method. This is because the driving circuits have to operate at high speed especially when a high gradation is to be obtained.
Another problem is that the amount of current flowing in the light emitting element is changed to change the luminance even when a constant voltage is applied to the light emitting element. In the digital method, the driving TFT operates as a switch for applying a constant voltage between the anode and the cathode of the light emitting element of each pixel to make the light emitting element emit light. However, characteristics of the light emitting element are changed by a temperature change in the surroundings of the display device and this causes the luminance to vary.
FIG. 26 is a graph showing current-voltage curves at different temperatures. The voltage (applied voltage in the graph) in the curves is the voltage between the electrodes (anode and cathode) of the light emitting element, and the current in the curves is the current flowing between the electrodes of the light emitting element. The temperatures are of the surroundings of the display device and denoted by T1, T2, and T3. T1 is higher than T2 and T2 is higher than T3.
In FIG. 26, the current flowing in the light emitting element is increased in amount as the temperature rises even when the voltage applied between the electrodes of the light emitting element is kept constant. Since the luminance of the light emitting element is substantially in proportion to the amount of current flowing in the light emitting element, a temperature rise causes a change in luminance of the light emitting element. An increase in power consumption is also caused.
In the above analog or digital method, analog or digital voltage signals are inputted to source signal lines to display an image. This method is called a voltage drive method. On the other hand, a method of displaying an image by inputting a current to source signal lines has been proposed. This one is called a current drive method.
The current drive method provides a display device in which light is emitted at a constant luminance irrespective of a change in temperature of the surroundings.
The structure of this display device is described below.
A pixel structured as shown in FIG. 3 has been proposed in order to obtain the display device that is not affected by a temperature change.
The pixel having this structure is characterized in that uneven display between pixels is greatly reduced if TFTs of the pixels have uniform characteristics.
The structure of the pixel shown in FIG. 3 is described below.
The pixel has a first switching TFT 402, a second switching TFT 403, a TFT 404, a TFT 405, a storage capacitor 406, and a light emitting element 407. The TFTs 404 and 405 constitute a current mirror circuit. The storage capacitor 406 is not always necessary if the device makes a positive use of gate capacitances of the TFTs 404 and 405. A detailed description is given below on the structure of this pixel.
A gate electrode of the first switching TFT 402 is connected to a gate signal line G. The first switching TFT 402 has a source region and a drain region one of which is connected to a source signal line S and the other of which is connected to a source region or drain region of the second switching TFT 403 and to a source region or drain region of the TFT 404. Of the source region and drain region of the second switching TFT 403, the one that is not connected to the first switching TFT is connected to gate electrodes of the TFTs 404 and 405 and to the storage capacitor 406. A gate electrode of the second switching TFT 403 is connected to a selection line C. One side of the TFT 404 that is not connected to the second switching TFT 403 is connected to a power supply line V. One side of the storage capacitor 406 that is not connected to the gate electrodes of the TFTs 404 and 405 is connected to the power supply line V. The TFT 405 has a source region and a drain region one of which is connected to the power supply line V and the other of which is connected to one of electrodes of the light emitting element 407.
A method of driving the pixel structured as above is described below. FIG. 4 is a circuit diagram showing the structure of a pixel portion in which pixels each structured as shown in FIG. 3 are arranged to form a matrix. The description is given with reference to the timing chart of FIG. 21. The reference symbols in FIGS. 3 and 4 are also used.
The first switching TFT and the second switching TFT here are n-channel TFTs. However, no problem arises if the first switching TFT and the second switching TFT are p-channel TFTs because they function as simple switches.
Signals are inputted to a gate signal line Gk (k is a natural number equal to or smaller than y) to turn the first switching TFT 402 0N. A selection line Ck also receives signals to turn the second switching TFT 403 0N, which causes a signal current Iin to flow to source signal lines S1 to Sx from the pixels. The signal current Iin flowing in the source signal lines is set to a given value by a source signal line driving circuit.
The signal current Iin flows first through the first switching TFT 402, the second switching TFT 403, and the storage capacitor 406 between the source signal line S and the power supply line V. As a result, electric charges are held in the storage capacitor 406. When the electric charges held push the gate/source voltage of the TFT 404 over the threshold, a current starts to flow through the TFT 404. After a sufficient period of time passes, the current flowing in the TFT 404 reaches the level of the signal current Iin. The gate voltage of the TFT 404 at this point is held in the storage capacitor 406.
The second switching TFT 403 connects the drain region of the TFT 404 to the gate electrode thereof. Therefore the gate/source voltage (gate voltage) of the TFT 404 is equal to the source/drain voltage thereof to make the TFT 404 operate in a saturation range. In a TFT that operates in a saturation range, the drain current takes an almost constant value once the gate voltage corresponding thereto is fixed.
The gate voltage of the TFT 404 is kept equal to the gate voltage of the TFT 405.
The TFT 404 and the TFT 405 that constitute a current mirror circuit have identical characteristics.
Accordingly, the signal current Iin flowing in the TFT 404 is equal to a current I inputted to the light emitting element 407 through the drain/source of the TFT 405 from the power supply line V.
After the gate voltage of when the signal current Iin flows in the TFT 404 is held in the storage capacitor 406, the second switching TFT 403 is turned OFF. If the first switching TFT 402 is also turned OFF at this point, it does not stop the TFTs 404 and 405 from maintaining the electric potential of their gate electrodes and the current I is kept inputted to the light emitting element 407. In this way the light emitting element continues to emit light at a luminance according to the current I, namely, the signal current Iin.
If an adjustment is made so that the next signal current Iin flows in the source signal line in the same pixel in the second frame period F2 after the first frame period is ended, the electric potential according to the new signal current Iin is held in the storage capacitor 406. The current inputted to the light emitting element 407 is therefore changed to a current I according to the new signal. Then the light emitting element 407 emits light at a luminance according to the signal current Iin.
Before allowing the signal current Iin for the next frame period to flow in the source/drain of the TFT 404, each pixel may discharge the voltage previously held in the storage capacitor, namely the previous gate voltage of the TFTs 404 and 405 that constitute a current mirror circuit. In order to discharge the electric charges held in the storage capacitor 406, electric potentials of two electrodes of the storage capacitor 406 are made equal to each other by, for example, connecting wiring lines using a switch or the like.
FIG. 20 is a block diagram of the display device that has pixels each structured as shown in FIGS. 3 and 4 when the device is driven in accordance with the timing chart of FIG. 21.
In FIG. 20, the display device is composed of a source signal line driving circuit 2001, a gate signal line driving circuit 2007a, a selection line driving circuit 2007b, and a pixel portion 2000. The source signal line driving circuit 2001 is composed of a shift register 2002, an LAT1 2003, an LAT2 2004, a DAC 2005, and a constant current circuit 2006. The shift register 2002 receives clock pulses CLK and start pulses SP and outputs sampling pulses. In response to the sampling pulses, the LAT1 2003 holds signal voltages of digital video signals VD in order.
The amount of information the digital video signals here have is n bits.
Digital video signals of the respective bits out of n bits are inputted to the LAT1 2003. Digital video signals inputted from the external are subjected to serial/parallel conversion in advance using an SPC (serial-to-parallel conversion circuit) or the like, and n bits signals are simultaneously inputted to the LAT1 2003. After signals for one horizontal period are all inputted to the LAT1 2003, the signals are then inputted to the LAT2 2004 at once in response to latch pulses LP. When the source signal line driving circuit for outputting signals to x source signal lines handles n-bit digital video signals, the LAT1 2003 and the LAT2 2004 each have to store xn bits digital signals.
The SPC (not shown in the drawing) for converting these signals may be formed on the same substrate on which the pixel portion is formed. Alternatively, the SPC may be an IC chip attached to the top face of the substrate on which the pixel portion is formed.
The n bits digital video signals VD associated with one source signal line are held in the LAT2 2004 and their signal voltages are inputted to the DAC 2005 to be converted into corresponding analog signal voltages.
The analog signal voltages obtained by the conversion are inputted to the constant current circuit 2006. The constant current circuit 2006 outputs a signal current according to the analog signal voltages to the source signal lines.
A circuit having a known structure can be used as the constant current circuit 2006 that outputs a constant current according to an inputted analog signal voltage.
The pixels structured as shown in FIG. 4 are thus driven in accordance with the timing chart of FIG. 21 to display an image.
An example of the display device using the current drive method is described as above.
In the above-described driving method that uses an analog signal current inputted to source signal lines to control a current inputted to a light emitting element, the value of the current inputted to the light emitting element is set. The method is therefore free from the problem of fluctuated luminance of the light emitting element which is caused by a change in temperature of the surroundings.
However, in the display device of the current drive method as above, the amount of current flowing in the circuits is increased as the gradation becomes higher to raise a new problem of increased power consumption.
In the case where an analog method is used in a display device of conventional voltage drive method, fluctuation in characteristics of TFTs of pixels causes the problem of uneven display.
In the case where a digital method and a time ratio gradation method are employed in a display device of conventional voltage drive method, one frame period has to be divided into many sub-frame periods in order to obtain a large gradation number. The driving circuits accordingly have to operate at high speed to raise the problem of increased power consumption.
When there is a large shift in temperature of the surroundings in which the display device is used, the temperature characteristic of the light emitting element is greatly changed to change the amount of current flowing in the light emitting element and make it difficult to keep the luminance of the display device constant.
On the other hand, a display device of conventional current drive method is not suitable for higher gradation.